1. Field of the Invention
The present invention relates to an image signal processing circuit advantageously employed for detection of a motion vector employed for image compression and encoding in digital image processing. More particularly, the invention relates to an image signal processing circuit for detecting a motion vector by carrying out a full search of the image data by a block-matching method.
The present invention is an improvement of the invention of the pending U.S. patent application Ser. No. 08/140,318 of the same assignee of this application.
2. Description of the Related Art
Among the methods in general commercial use for the detection of motion vectors as used in image compression and encoding in processing digital image signals, there is a block-matching method and a gradient method.
An explanation will be made here of the block-matching method. The block-matching method is extensively used for motion compensation prediction in image compression and encoding.
In the block-matching method, picture frame data or field data are divided into smaller blocks. The size of each block used at this time is in general 8.times.8 pixels or 16.times.16 pixels. In this method, processing for detection of a motion vector means, basically, detecting from which region of a previous frame a certain block (called a reference block) of a current frame has moved. Specifically, detection of a motion vector involves processing to detect the block bearing the strongest resemblance to a reference block Bp of a current frame Fp from a group of candidate blocks Bb in a search range E of the previous frame Fb and detecting the shift in position between the detected candidate block Bb and the reference block Bp as the motion vector, as shown for example, in FIG. 5.
Here, a reference block is the block subjected to the motion vector detection processing at any one point of time in the latest frame of a color motion picture (current frame), while a candidate block is the block focused on in the calculation of the difference from the frame just before the current frame (previous frame).
The block bearing the strongest resemblance to the reference block Bp is determined as follows in the processing for detection of a motion vector.
As a first step, the difference is taken between each pixel data c of a given candidate block Bb and the corresponding pixel data r of the reference block Bp and an evaluation value is found represented by the differences. For example, a sum of the absolute values of the differences (hereinafter referred to as the "absolute differences") or a sum of the square value of the differences (hereinafter after referred to as the "squared differences").
As a second step, the operation of the first step is performed for each other of the other candidate blocks Bb within the search range E and the block which gives the smallest sum of the absolute differences is found. The candidate block Bb giving the smallest the sum of the absolute differences or sum of the squared differences is adopted as the block bearing the strongest resemblance to the reference block Bp.
Specifically, if the block size of the reference block Bp is M.times.N pixels and the number of the candidate blocks Bb is K.times.L, the above-described processing detect of a movement vector may be represented by the following formulas (1) and (2): ##EQU1##
Note that the sum of the absolute differences D(i,j) is found in formula (1) and formula (2), not the sum of squared differences. Further, the r in formula (1) represents the pixel data of the reference block Bp of the current frame, while the c in formula (1) represents the pixel data of one of the candidate blocks of the previous frame. Further, the (x,y) in formula (2) means the pixel position (i,j) which gives the least sum of the absolute differences (minD(i,j)). The (x,y) in formula (2) represents the movement vector MV(x,y).
In view of the above, in the case of a block size of a reference block Bp of 4.times.4 pixels and the number of the candidate block Bp of 7.times.7, in the above-described example of FIG. 5 in which the sum of the absolute differences D(5,3) becomes the smallest, the movement vector MV is given as (5,3):MV(5,3).
Next, an explanation will be made of the circuit configuration for processing to detect of a motion vector in frame units (hereinafter referred to as "processing for detection of a motion vector of a frame"). First, to help explain the circuit configuration, an explanation will be made of an example of the processing for detection of a motion vector. The circuit configuration and control system will be explained with reference to this example.
Here, as one example, an explanation will be made with reference to FIG. 6 of processing for detection of a motion vector in the case where a block size of the reference block Bp has 3.times.4 pixels and the number of candidate blocks Bb is 3.times.4. Note that in FIG. 6, the pixel data r of a reference block Bp of the current frame Fp have the English lower case letters a, b, c, . . . affixed as subscripts (r.sub.a, r.sub.b, r.sub.c, . . . ). Further, the pixel data c of the previous frame Fb have the numerals 0, 1, 2, . . . affixed as subscripts (c.sub.0, c.sub.1, c.sub.2, . . . ). Below, an explanation will be made of the routine for the processing for detection of a motion vector of a frame with reference to FIG. 6.
As a first step of the processing, the calculations of the following formulas (3) to (14) are performed on the pixel data c (c.sub.0 to c.sub.34) of all the candidate blocks Bb0 (of which there are 12) in the search range E0 for a reference block Bp0 based on the above-mentioned formula (1) to obtain the sum of the absolute differences, D(i,j), where o.ltoreq.i.ltoreq.2, 0.ltoreq.j.ltoreq.3. EQU D(0,0)=.vertline.r.sub.a -c.sub.0 .vertline.+.vertline.r.sub.b -c.sub.1 .vertline.+.vertline.r.sub.c -c.sub.2 .vertline.+.vertline.r.sub.d -c.sub.3 .vertline.+.vertline.r.sub.e -c.sub.7 .vertline.+ - - - +.vertline.r.sub.l -c.sub.17 .vertline. (3) EQU D(0,1)=.vertline.r.sub.a -c.sub.1 .vertline.+.vertline.r.sub.b -c.sub.2 .vertline.+.vertline.r.sub.c -c.sub.3 .vertline.+.vertline.r.sub.d -c.sub.4 .vertline.+.vertline.r.sub.e -c.sub.8 .vertline.+ - - - +.vertline.r.sub.l -c.sub.18 .vertline. (4) EQU D(0,2)=.vertline.r.sub.a -c.sub.2 .vertline.+.vertline.r.sub.b -c.sub.3 .vertline.+.vertline.r.sub.c -c.sub.4 .vertline.+.vertline.r.sub.d -c.sub.5 .vertline.+.vertline.r.sub.e -c.sub.9 .vertline.+ - - - +.vertline.r.sub.l -c.sub.19 .vertline. (5) EQU D(0,3)=.vertline.r.sub.a -c.sub.3 .vertline.+.vertline.r.sub.b -c.sub.4 .vertline.+.vertline.r.sub.c -c.sub.5 .vertline.+.vertline.r.sub.d -c.sub.6 .vertline.+.vertline.r.sub.e -c.sub.10 .vertline.+ - - - +.vertline.r.sub.l -c.sub.20 .vertline. (6) EQU D(1,0)=.vertline.r.sub.a -c.sub.7 .vertline.+.vertline.r.sub.b -c.sub.8 .vertline.+.vertline.r.sub.c -c.sub.9 .vertline.+.vertline.r.sub.d -c.sub.10 .vertline.+.vertline.r.sub.e -c.sub.14 .vertline.+ - - - +.vertline.r.sub.l -c.sub.24 .vertline. (7) EQU D(1,1)=.vertline.r.sub.a -c.sub.8 .vertline.+.vertline.r.sub.b -c.sub.9 .vertline.+.vertline.r.sub.c -c.sub.10 .vertline.+.vertline.r.sub.d -c.sub.11 .vertline.+.vertline.r.sub.e -c.sub.15 .vertline.+ - - - +.vertline.r.sub.l -c.sub.25 .vertline. (8) EQU D(1,2)=.vertline.r.sub.a -c.sub.9 .vertline.+.vertline.r.sub.b -c.sub.10 .vertline.+.vertline.r.sub.c -c.sub.11 .vertline.+.vertline.r.sub.d -c.sub.12 .vertline.+.vertline.r.sub.e -c.sub.16 .vertline.+ - - - +.vertline.r.sub.l -c.sub.26 .vertline. (9) EQU D(1,3)=.vertline.r.sub.a -c.sub.10 .vertline.+.vertline.r.sub.b -c.sub.11 .vertline.+.vertline.r.sub.c -c.sub.12 .vertline.+.vertline.r.sub.d -c.sub.13 .vertline.+.vertline.r.sub.e -c.sub.17 .vertline.+ - - - +.vertline.r.sub.l -c.sub.27 .vertline. (10) EQU D(2,0)=.vertline.r.sub.a -c.sub.14 .vertline.+.vertline.r.sub.b -c.sub.15 .vertline.+.vertline.r.sub.c -c.sub.16 .vertline.+.vertline.r.sub.d -c.sub.17 .vertline.+.vertline.r.sub.e -c.sub.21 .vertline.+ - - - +.vertline.r.sub.l -c.sub.31 .vertline. (11) EQU D(2,1)=.vertline.r.sub.a -c.sub.15 .vertline.+.vertline.r.sub.b -c.sub.16 .vertline.+.vertline.r.sub.c -c.sub.17 .vertline.+.vertline.r.sub.d -c.sub.18 .vertline.+.vertline.r.sub.e -c.sub.22 .vertline.+ - - - +.vertline.r.sub.l -c.sub.32 .vertline. (12) EQU D(2,2)=.vertline.r.sub.a -c.sub.16 .vertline.+.vertline.r.sub.b -c.sub.17 .vertline.+.vertline.r.sub.c -c.sub.18 .vertline.+.vertline.r.sub.d -c.sub.19 .vertline.+.vertline.r.sub.e -c.sub.23 .vertline.+ - - - +.vertline.r.sub.l -c.sub.33 .vertline. (13) EQU D(2,3)=.vertline.r.sub.a -c.sub.17 .vertline.+.vertline.r.sub.b -c.sub.18 .vertline.+.vertline.r.sub.c -c.sub.19 .vertline.+.vertline.r.sub.d -c.sub.20 .vertline.+.vertline.r.sub.e -c.sub.24 .vertline.+ - - - +.vertline.r.sub.l -c.sub.34 .vertline. (14)
A detailed description of the sum of the squared differences will be omitted since it is sufficient if the terms of the absolute differences are made (r-c).sup.2.
Next, as the second step of the processing, the sum of the absolute differences minD(i,j) giving the smallest value is found from among all the sums of absolute differences D(i,j) (0.ltoreq.i&lt;2, 0.ltoreq.j&lt;3) found in the above-mentioned first step of the processing based on the above-mentioned formula (2) so as to obtain the motion vector MV(x,y).
As the third step of the processing, calculations are performed based on formula (1), in the same way as in the first step of the processing, for the pixel data r.sub.a' to r.sub.t' of the reference block Bp1 adjoining the reference block Bp0 and the pixel data c.sub.21 to c.sub.55 of all the candidate blocks Bb1 (of which there are 12 in the embodiment) in the search range E1 of the reference block Bp1 so as to find the sums D'(i,j) of absolute differences (0.ltoreq.i&lt;2, 0.ltoreq.j&lt;3).
Then, as a fourth step of the processing, the sum of the absolute differences minD'(i,j) giving the smallest value is found from among all the sums of the absolute differences D'(i,j) (0.ltoreq.i&lt;2, 0.ltoreq.j&lt;3) found in the above-mentioned third step of the processing based on the above-mentioned formula (2) so as to obtain the motion vector MV(x,y).
Finally, as a fifth step of the processing, the above procedure is repeated for all the other reference blocks Bp of the current frame Fp in the same way to find the motion vector MV(x,y).
The processing for detection of a motion vector explained above is realized by the circuit configuration shown in FIG. 1, FIG. 2, and FIG. 3.
Here, FIG. 1 shows the overall configuration of a motion vector detection circuit, that is, an image signal processing circuit for detection of a motion vector. In FIG. 1, the image signal processing circuit is comprised of a plurality of processing units (PE) 10 to 21, a plurality of pixel data storage registers (REG) 22 to 38, and a plurality of multiplexer-equipped pixel data storage registers (M&R) 39 to 44 connected with each other.
That is, in FIG. 1, the pixel data r of a reference block Bp are supplied to a terminal 1 and are then sent to the cascade-connected processing units 10 to 21. Further, the pixel data c of the candidate blocks Bb of the upper half of the search range E, for example, are supplied to the terminal 2 and sent to the input terminal of the first-stage register 22 of the cascade-connected pixel data storage registers 22 to 25 to be successively stored in the pixel data storage registers 22 to 25.
The outputs of the pixel data storage registers 22 to 25 are also supplied to the corresponding processing units 10 to 13 among the above-mentioned processing units 10 to 21. The output of the processing unit 13 among the processing units 10 to 13 is supplied to the input terminal of the first-stage register 30 of the cascade-connected pixel data storage registers 30 to 32 to be successively stored by these pixel data storage registers 30 to 32. The outputs of the pixel data storage registers 30 to 32 are also supplied to the corresponding processing units 15 to 17 among the processing units 10 to 21.
Further, the output of the processing unit 17 among the processing units 15 to 17 is supplied to the input terminal of the first-stage register 33 of the cascade-connected pixel data storage registers 33 to 35 to be successively stored by these pixel data storage registers 33 to 35. The outputs of these pixel data storage registers 33 to 35 are supplied to the corresponding processing units 19 to 21 among the above-mentioned processing units 10 to 12.
Further, the pixel data c of the candidate blocks Bb of the lower half of the search range E, for example, are supplied to the terminal 3 and sent to the input terminal of the first-stage register 26 of the cascade-connected pixel data storage registers 26 to 29 to be successively stored in the pixel data storage registers 26 to 29. The output of the pixel data storage register 27 among the pixel data storage registers 26 to 29 is also supplied to the pixel data storage register 36, the output of the register 28 is supplied to the other input terminal of the multiplexer-equipped pixel data storage register 39, to the first input terminal of which the output of the register 36 is supplied, and the output of the register 29 is also supplied to the other input terminal of the multiplexer-equipped pixel data storage register 40, to the first input terminal of which the output of the register 39 is supplied.
The output of the multiplexer-equipped pixel data storage register 40 is supplied to the input terminal of the processing unit 10 among the processing units 10 to 21. The output of the processing unit 10 is supplied to the next processing unit 11 and is supplied to the input terminal of the pixel data storage register 37. The output of the register 37 is supplied to the other input terminal of the multiplexer-equipped pixel data storage register 41, to the first input terminal of which the output of the processing unit 11 is supplied, and the output of the register 41 is supplied to the other input terminal of the multiplexer-equipped pixel data storage register 42, to the first input terminal of which the output of the processing unit 12 is supplied. Further, the output of the processing unit 13 is supplied to the pixel data storage register 30 and is supplied to the processing unit 14 as well.
Further, the output of the processing unit 14 is supplied to the next processing unit 15 and is supplied to the input terminal of the pixel data storage register 38. The output of the register 38 is supplied to the other input terminal of the multiplexer-equipped pixel data storage register 43, to the first input terminal of which the output of the processing unit 15 is supplied, and the output of the register 43 is supplied to the other input terminal of the multiplexer-equipped pixel data storage register 44, to the first input terminal of which the output of the processing unit 16 is supplied. Further, the output of the processing unit 17 is supplied to the pixel data storage register 33 and is supplied to the processing unit 18 as well.
Specifically, each of the processing units 10 to 21 shown in FIG. 1 is constructed as shown in FIG. 2. In FIG. 2, outputs of the other processing units or outputs of the pixel data storage registers of FIG. 1 are supplied to a terminal 51, while outputs of the other processing units or outputs of the multiplexer-equipped pixel data storage registers shown in FIG. 1 are supplied to a terminal 55. The input signals supplied to the terminals 51 and 55 are multiplexed by a multiplexer (MPX) 57, then are suitably switched and then supplied to pixel data storage register 58. The output of the pixel data storage register 58 is output at output terminals 52 and 54, while being supplied to an input terminal of an absolute difference processor (.vertline.r-c.vertline.) 59. The other input terminal of the absolute difference processor 59 is supplied with the pixel data r of the reference block Bp via the terminal 1 of FIG. 1 and a terminal 53. An output of the processor 59 is supplied to an accumulator (ACC) 60, where it is accumulated by the accumulator 60 and then the result output as the sum of the absolute differences D(i,j) at a terminal 56.
On the other hand, each of the multiplexer-equipped pixel data storage registers 39 to 44 shown in FIG. 1 is constructed as shown in FIG. 3. In FIG. 3, an output of the pixel data storage register or the multiplexer-equipped pixel data storage register of the preceding stage shown in FIG. 1 is supplied to a terminal 72, while an output of the associated pixel data storage register or the processing unit shown in FIG. 1 is supplied via a terminal 54 shown in FIG. 2. The input signals supplied to the terminals 72 and 73 are multiplexed by a multiplexer 75 and are suitably switched, then are supplied to a pixel data storage. register 76. An output of the pixel data storage register 76 is supplied to a later stage circuit via a terminal 71.
A control method for realizing the processing for detection of a motion vector using the circuit configuration shown in FIGS. 2 and 3 is hereinafter explained by referring to FIG. 4 showing control timings for motion vector detection.
As shown in FIG. 4, the pixel data r of the reference block Bp are given to all of the processing units each clock cycle. That is, each processing unit performs processing on the same pixel data r of a given reference block Bp during a given clock cycle.
On the other hand, the pixel data c of the candidate blocks Bb are divided into two regions, the upper half and lower half of the search range E, and then successively supplied to the input terminals 2, 3, shown in FIG. 1. Also, the pixel data c of the candidate blocks Bb are supplied at each clock cycle to a later stage pixel data storage register. However, they are transmitted to the pixel data storage register 58 of the processing unit shown in FIG. 2 once every four clock cycles. In this manner, each processing unit performs processing on different pixel data c of the candidate blocks Bb during a given clock cycle, as shown in FIG. 4.
In the above processing circuit, the sums of the absolute differences are all output from the respective processing units every 12 clock cycles (output from the output terminal 56 shown in FIG. 1) as a result of the above-described control. The motion vector MV(x,y) is found by comparing the magnitudes of these sums D(i,j). Note that since the accumulator 60 shown in FIG. 2 immediately starts the accumulation of the sums of the absolute differences D(i,j) for the next reference block Bp during the next clock cycle, it is necessary to store the sums of the absolute differences D(i,j) once in the respective registers before proceeding to comparison as mentioned above.
The above explanation is of the circuit configuration for processing for detection of a motion vector of a frame.
Below, an explanation will be made of a circuit configuration able to handle also processing for detection of a motion vector in units of fields (hereinafter referred to as "processing for detection of a motion vector for a field"). In this processing for detection of a motion vector for a field, three motion vectors, one each for the even number field, odd number field, and frame will be obtained. Here, use will once again be made of the example used for the explanation of the processing for detection of a motion vector of a frame (see FIG. 6).
Here, assume that the pixel data r.sub.a to r.sub.t of the reference block Bp0 are divided into the following two groups corresponding to the even number field and odd number field. That is, for example, they are divided into the group of (r.sub.a, r.sub.c, r.sub.e, r.sub.g, r.sub.i, r.sub.k) for the even number field and the group of (r.sub.b, r.sub.d, r.sub.f, r.sub.h, r.sub.j, r.sub.l) for the odd number field.
Below, an explanation will be made of the routine for the processing for detection of motion vectors for the above fields, with reference to FIG. 6.
First, an explanation will be made of the case of the even number field. In this case, the pixel data r of the even number field of a reference block Bp0 and the pixel data c.sub.0 to c.sub.34 of all the candidate blocks Bb0 (of which there are 12) in the search range E0 for the reference block Bp0 are used to perform the calculation shown in the following formulas (15) to (26) based on formula (1) and thereby find the sum of the absolute differences D.sub.e (i,j) at the even number field (0.ltoreq.i&lt;2, 0.ltoreq.j&lt;3): EQU D.sub.e (0,0)=.vertline.r.sub.a -c.sub.0 .vertline.+.vertline.r.sub.c -c.sub.2 .vertline.+.vertline.r.sub.e -c.sub.7 .vertline.+.vertline.r.sub.g -c.sub.9 .vertline.+.vertline.r.sub.i -c.sub.14 .vertline.+.vertline.r.sub.k -c.sub.16 .vertline.(15) EQU D.sub.e (0,1)=.vertline.r.sub.a -c.sub.1 .vertline.+.vertline.r.sub.c -c.sub.3 .vertline.+.vertline.r.sub.e -c.sub.8 .vertline.+.vertline.r.sub.g -c.sub.10 .vertline.+.vertline.r.sub.i -c.sub.15 .vertline.+.vertline.r.sub.k -c.sub.17 .vertline.(16) EQU D.sub.e (0,2)=.vertline.r.sub.a -c.sub.2 .vertline.+.vertline.r.sub.c -c.sub.4 .vertline.+.vertline.r.sub.e -c.sub.9 .vertline.+.vertline.r.sub.g -c.sub.11 .vertline.+.vertline.r.sub.i -c.sub.16 .vertline.+.vertline.r.sub.k -c.sub.18 .vertline.(17) EQU D.sub.e (0,3)=.vertline.r.sub.a -c.sub.3 .vertline.+.vertline.r.sub.c -c.sub.5 .vertline.+.vertline.r.sub.e -c.sub.10 .vertline.+.vertline.r.sub.g -c.sub.12 .vertline.+.vertline.r.sub.i -c.sub.17 .vertline.+.vertline.r.sub.k -c.sub.19 .vertline.(18) EQU D.sub.e (1,0)=.vertline.r.sub.a -c.sub.7 .vertline.+.vertline.r.sub.c -c.sub.9 .vertline.+.vertline.r.sub.e -c.sub.14 .vertline.+.vertline.r.sub.g -c.sub.16 .vertline.+.vertline.r.sub.i -c.sub.21 .vertline.+.vertline.r.sub.k -c.sub.23 .vertline.(19) EQU D.sub.e (1,1)=.vertline.r.sub.a -c.sub.8 .vertline.+.vertline.r.sub.c -c.sub.10 .vertline.+.vertline.r.sub.e -c.sub.15 .vertline.+.vertline.r.sub.g -c.sub.17 .vertline.+.vertline.r.sub.i -c.sub.22 .vertline.+.vertline.r.sub.k -c.sub.24 .vertline.(20) EQU D.sub.e (1,2)=.vertline.r.sub.a -c.sub.9 .vertline.+.vertline.r.sub.c -c.sub.11 .vertline.+.vertline.r.sub.e -c.sub.16 .vertline.+.vertline.r.sub.g -c.sub.18 .vertline.+.vertline.r.sub.i -c.sub.23 .vertline.+.vertline.r.sub.k -c.sub.25 .vertline.(21) EQU D.sub.e (1,3)=.vertline.r.sub.a -c.sub.10 .vertline.+.vertline.r.sub.c -c.sub.12 .vertline.+.vertline.r.sub.e -c.sub.17 .vertline.+.vertline.r.sub.g -c.sub.19 .vertline.+.vertline.r.sub.i -c.sub.24 .vertline.+.vertline.r.sub.k -c.sub.26 .vertline.(22) EQU D.sub.e (2,0)=.vertline.r.sub.a -c.sub.14 .vertline.+.vertline.r.sub.c -c.sub.16 .vertline.+.vertline.r.sub.e -c.sub.21 .vertline.+.vertline.r.sub.g -c.sub.23 .vertline.+.vertline.r.sub.i -c.sub.28 .vertline.+.vertline.r.sub.k -c.sub.30 .vertline.(23) EQU D.sub.e (2,1)=.vertline.r.sub.a -c.sub.15 .vertline.+.vertline.r.sub.c -c.sub.17 .vertline.+.vertline.r.sub.e -c.sub.22 .vertline.+.vertline.r.sub.g -c.sub.24 .vertline.+.vertline.r.sub.i -c.sub.29 .vertline.+.vertline.r.sub.k -c.sub.31 .vertline.(24) EQU D.sub.e (2,2)=.vertline.r.sub.a -c.sub.16 .vertline.+.vertline.r.sub.c -c.sub.18 .vertline.+.vertline.r.sub.e -c.sub.23 .vertline.+.vertline.r.sub.g -c.sub.25 .vertline.+.vertline.r.sub.i -c.sub.30 .vertline.+.vertline.r.sub.k -c.sub.32 .vertline.(25) EQU D.sub.e (2,3)=.vertline.r.sub.a -c.sub.17 .vertline.+.vertline.r.sub.c -c.sub.19 .vertline.+.vertline.r.sub.e -c.sub.24 .vertline.+.vertline.r.sub.g -c.sub.26 .vertline.+.vertline.r.sub.i -c.sub.31 .vertline.+.vertline.r.sub.k -c.sub.33 .vertline.(26)
Next, an explanation will be made of the case of the odd number field. In this case, in the same way as the case of the even number field, the pixel data c.sub.0 to c.sub.34 of all the candidate blocks Bb0 (of which there are 12) in the search range E0 for a reference block Bp0 are used perform the calculation shown in the following formulas (27) to (38) based on formula (1) for the pixel data r of the odd number field of the reference block Bp0 and thereby find the sum of the absolute differences D.sub.o (i,j) the odd number field (0.ltoreq.i&lt;2, 0.ltoreq.j&lt;3): EQU D.sub.o (0,0)=.vertline.r.sub.a -c.sub.1 .vertline.+.vertline.r.sub.d -c.sub.3 .vertline.+.vertline.r.sub.f -c.sub.8 .vertline.+.vertline.r.sub.h -c.sub.10 .vertline.+.vertline.r.sub.j -c.sub.15 .vertline.+.vertline.r.sub.l -c.sub.17 .vertline.(27) EQU D.sub.o (0,1)=.vertline.r.sub.b -c.sub.2 .vertline.+.vertline.r.sub.d -c.sub.4 .vertline.+.vertline.r.sub.f -c.sub.9 .vertline.+.vertline.r.sub.h -c.sub.11 .vertline.+.vertline.r.sub.j -c.sub.16 .vertline.+.vertline.r.sub.l -c.sub.18 .vertline.(28) EQU D.sub.o (0,2)=.vertline.r.sub.b -c.sub.3 .vertline.+.vertline.r.sub.d -c.sub.5 .vertline.+.vertline.r.sub.f -c.sub.10 .vertline.+.vertline.r.sub.h -c.sub.12 .vertline.+.vertline.r.sub.j -c.sub.17 .vertline.+.vertline.r.sub.l -c.sub.19 .vertline.(29) EQU D.sub.o (0,3)=.vertline.r.sub.b -c.sub.4 .vertline.+.vertline.r.sub.d -c.sub.6 .vertline.+.vertline.r.sub.f -c.sub.11 .vertline.+.vertline.r.sub.h -c.sub.13 .vertline.+.vertline.r.sub.j -c.sub.18 .vertline.+.vertline.r.sub.l -c.sub.20 .vertline.(30) EQU D.sub.o (1,0)=.vertline.r.sub.b -c.sub.8 .vertline.+.vertline.r.sub.d -c.sub.10 .vertline.+.vertline.r.sub.f -c.sub.15 .vertline.+.vertline.r.sub.h -c.sub.17 .vertline.+.vertline.r.sub.j -c.sub.22 .vertline.+.vertline.r.sub.l -c.sub.24 .vertline.(31) EQU D.sub.o (1,1)=.vertline.r.sub.b -c.sub.9 .vertline.+.vertline.r.sub.d -c.sub.11 .vertline.+.vertline.r.sub.f -c.sub.16 .vertline.+.vertline.r.sub.h -c.sub.18 .vertline.+.vertline.r.sub.j -c.sub.23 .vertline.+.vertline.r.sub.l -c.sub.25 .vertline.(32) EQU D.sub.o (1,2)=.vertline.r.sub.b -c.sub.10 .vertline.+.vertline.r.sub.d -c.sub.12 .vertline.+.vertline.r.sub.f -c.sub.17 .vertline.+.vertline.r.sub.h -c.sub.19 .vertline.+.vertline.r.sub.j -c.sub.24 .vertline.+.vertline.r.sub.l -c.sub.26 .vertline.(33) EQU D.sub.o (1,3)=.vertline.r.sub.b -c.sub.11 .vertline.+.vertline.r.sub.d -c.sub.13 .vertline.+.vertline.r.sub.f -c.sub.18 .vertline.+.vertline.r.sub.h -c.sub.20 .vertline.+.vertline.r.sub.j -c.sub.25 .vertline.+.vertline.r.sub.l -c.sub.27 .vertline.(34) EQU D.sub.o (2,0)=.vertline.r.sub.b -c.sub.15 .vertline.+.vertline.r.sub.d -c.sub.17 .vertline.+.vertline.r.sub.f -c.sub.22 .vertline.+.vertline.r.sub.h -c.sub.24 .vertline.+.vertline.r.sub.j -c.sub.29 .vertline.+.vertline.r.sub.l -c.sub.31 .vertline.(35) EQU D.sub.o (2,1)=.vertline.r.sub.b -c.sub.16 .vertline.+.vertline.r.sub.d -c.sub.18 .vertline.+.vertline.r.sub.f -c.sub.23 .vertline.+.vertline.r.sub.h -c.sub.25 .vertline.+.vertline.r.sub.j -c.sub.30 .vertline.+.vertline.r.sub.l -c.sub.32 .vertline.(36) EQU D.sub.o (2,2)=.vertline.r.sub.b -c.sub.17 .vertline.+.vertline.r.sub.d -c.sub.19 .vertline.+.vertline.r.sub.f -c.sub.24 .vertline.+.vertline.r.sub.h -c.sub.26 .vertline.+.vertline.r.sub.j -c.sub.31 .vertline.+.vertline.r.sub.l -c.sub.33 .vertline.(37) EQU D.sub.o (2,3)=.vertline.r.sub.b -c.sub.18 .vertline.+.vertline.r.sub.d -c.sub.20 .vertline.+.vertline.r.sub.f -c.sub.25 .vertline.+.vertline.r.sub.h -c.sub.27 .vertline.+.vertline.r.sub.j -c.sub.32 .vertline.+.vertline.r.sub.l -c.sub.34 .vertline.(38)
Finally, for the frame, in the same way as the case of the processing for detection of a motion vector for a frame mentioned above, calculation of the formulas (3) to (14) is performed based on formula (1) for the pixel data c (c.sub.0 to c.sub.34) of all the candidate blocks in the search range E0 for the reference block Bp0 to find the sum of absolute differences D(i,j) of the frame (0.ltoreq.i&lt;2, 0.ltoreq.j&lt;3).
Next, the smallest sum of the absolute differences minD.sub.e (i,j) is found based on formula (2) from all the sums of the absolute differences D.sub.e (i,j) at the even number field to obtain the motion vector MV.sub.e (x,y) at the even number field.
Further, the smallest sum of the absolute differences minD.sub.o (i,j) is found based on formula (2) from all the sums of the absolute differences D.sub.o (i,j) at the odd number field to obtain the motion vector MV.sub.o (x,y) at the odd number field.
Similarly, the smallest sum of the absolute differences minD(i,j) is found based on formula (2) from all the sums of absolute differences D(i,j) at a frame to obtain the motion vector MV(x,y) at the frame.
Next, in the same way as above, the sum of the absolute differences D'.sub.e (i,j) at the even number field (0.ltoreq.i&lt;2, 0.ltoreq.j&lt;3), the sum of the absolute differences D'.sub.o (i,j) at the odd number field (0.ltoreq.i&lt;2, 0.ltoreq.j&lt;3), and the sum of the absolute differences D'(i,j) at the frame (0.ltoreq.i&lt;2, 0.ltoreq.j&lt;3) are found based on formula (1) for the pixel data r.sub.a' to r.sub.t' of the reference block Bp1 adjoining the reference block Bp0 and the pixel data c.sub.21 to c.sub.55 of all the candidate blocks Bb1 (of which there are 12) in the search range E1 of the reference block Bp1.
Here, the smallest sums of absolute differences D'.sub.e (i,j), minD'.sub.o (i,j), and minD'(i,j) are found based on formula (2) for the thus found sums of absolute differences D'.sub.e (i,j) (0.ltoreq.i&lt;2, 0.ltoreq.j&lt;3), D'.sub.o (i,j) (0.ltoreq.i&lt;2, 0.ltoreq.j&lt;3), and D'(i,j) (0.ltoreq.i&lt;2, 0.ltoreq.j&lt;3) to obtain the three types of motion vectors MV.sub.e (x,y), MV.sub.o (x,y), and MV(x,y) at the even number field, odd number field, and frame, respectively.
Below, in the same way, the above operation is repeated for all the other reference blocks Bp in the current frame Fp to find the three types of motion vectors MV.sub.e (x,y), MV.sub.o (x,y), and MV(x,y) at the even number field, odd number field, and frame.
The above processing for detection of a motion vector of a field is also realized by the circuit configuration shown in FIGS. 1, 2, and 3. That is, three of the motion vector detection circuits (processing circuits) of the configurations of FIGS. 1, 2, and 3 are provided and processing for detection of the motion vector at an even number field, processing for detection of the motion vector at an odd number field, and processing for detection of the motion vector at a frame are performed separately by these three motion vector detection circuits.
As explained above, with this circuit configuration for processing for detection of a motion vector for a field, the sums of the absolute differences at the even number field, odd number field, and frame are found by separately provided circuits. Since it is necessary to provide three motion vector detection circuits corresponding to the even number field, odd number field, and frame to perform the processing for detection of motion vectors, the amount of hardware increases.
In addition, since three motion vector detection circuits have to be provided to perform the processing for detection of the motion vector of a field, it becomes necessary to separately supply each of these three circuits with the pixel data of the reference block and the pixel data of the candidate blocks. Accordingly, compared with the circuit configuration in the case of performing processing for detection of the motion vector of just a frame, explained earlier, the circuit configuration for the processing for detection of a motion vector of a field requires additional external circuits and becomes more complicated. Therefore, an increase in the number of ports of the frame memory supplying the pixel data to the motion vector detection circuits is caused.
Further, the processing for detection of a motion vector by the block-matching method had been performed based on only one of a number of signal elements of a reference block of the current frame and the candidate blocks of the previous frame, for example, the luminance signal. Even if the luminance signal components of the pixels of a reference block and candidate block resemble each other, however, it is possible that other signal components, for example, the chrominance signals, will completely differ. Accordingly, when searching for the candidate block with the strongest resemblance to the reference block based on just the luminance signal, a candidate block with a completely different image may end up detected as the candidate block with the strongest resemblance.
When erroneously detecting the candidate block with the strongest resemblance in this way, the encoding efficiency of the compression and encoding of the motion picture information after compensation by a motion vector falls.
Further, as the search range in the previous frame is increased to improve the encoding efficiency, the likely resemblance of the luminance signals of a reference block and a candidate block also increases. But the chance of erroneously detecting a candidate block with completely different chrominance signals as the candidate block with the strongest resemblance also increases.
Accordingly, there is the problem that despite the broadening of the search range for improving the encoding efficiency, there is a change of a reverse phenomenon occurring of reduction of the encoding efficiency compared with the case of a narrower search range.